TPIC5423L datasheet(8/11 Pages) TI

Part #	TPIC5423L

Description	4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY

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TPIC5423L

4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL

POWER DMOS ARRAY

SLIS045 – NOVEMBER 1994

2–8

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

SOURCE-TO-DRAIN DIODE CURRENT

vs

SOURCE-TO-DRAIN VOLTAGE

VSD – Source-to-Drain Voltage – V

CAPACITANCE

vs

DRAIN-TO-SOURCE VOLTAGE

VDS – Drain-to-Source Voltage – V

0.6

0.4

0.2

0.1

1

2

4

10

6

0.1

10

1

TJ = – 40°C

TJ = 25°C

TJ = 75°C

TJ = 150°C

TJ = 125°C

VGS = 0

200

160

80

40

0

360

120

0

4

8

121620

24

280

240

320

400

28

32

36

40

VGS = 0

f = 1 MHz

TJ = 25°C

Ciss

Coss

Crss

CisS(0) = 301 pF

Coss(0) = 384 pF

Crss(0) = 144 pF

Figure 11

Figure 12

DRAIN-TO-SOURCE VOLTAGE AND

GATE-TO-SOURCE VOLTAGE

vs

GATE CHARGE

Qg – Gate Charge – nC

6

4

2

0

8

10

12

30

20

10

0

01

2

40

50

60

34

6

7

5

ID = 0.625 A

TJ = 25°C

See Figure 3

VDD = 20 V

VDD = 30 V

VDD = 48 V

VDD = 20 V

REVERSE-RECOVERY TIME

vs

REVERSE di/dt

Reverse di/dt – A/

µs

75

50

25

0

100

200

100

125

150

300

400

500

600

VDS = 48 V

VGS = 0

IS = 0.625 A

TJ = 25°C

See Figure 1

Z1, Z2, Z3, and Z4

D1, D2, D3, and D4

Figure 13

Figure 14

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