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CX74063-34 Datasheet(PDF) 9 Page - Skyworks Solutions Inc. |
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CX74063-34 Datasheet(HTML) 9 Page - Skyworks Solutions Inc. |
9 / 62 page Data Sheet I CX74063-34/-35/-36 Skyworks Solutions, Inc., Proprietary and Confidential 9 103116C [781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM NOVEMBER 25, 2003 Receive Section LNA and Quadrature Demodulator Three separate LNAs are integrated to address different bands of operation. These LNAs have separate single-ended inputs, which are externally matched to 50 Ω. The gain is switchable between high (i.e., 15 dB typical) and low (i.e., –5 dB GSM, –7 dB DCS, and –5 dB PCS typical) settings. The LNA outputs feed into a quadrature demodulator that downconverts the RF signals directly to baseband. Two external 470 pF capacitors are required at the demodulator output to suppress the out-of- band blockers. Baseband Section An off-chip capacitor and three fixed poles of on-chip, low pass filtering provide rejection of strong in- and out-of-band interferers. In addition, a tunable, four-pole gmC filter provides rejection of the adjacent channel blockers. Incorporated within the fixed-pole filters are two switchable gain stages of 18 dB and 12 dB gain steps, respectively. There is an additional programmable gain amplifier with a gain range from 0 to + 34 dB, selectable in 2 dB steps in the four-pole tunable filter. The final filter output feeds an amplifier with a gain range from 0 to 30 dB, selectable in 6 dB steps. There is an additional gain stage on the four-pole tunable filter output, the auxiliary gain stage, selectable at 0 dB or + 6 dB. The gain control ranges are shown in Figure 3. Recommended combinations of individual block gain settings are shown in Table 22 for GSM900, Table 23 for DCS1800, and Table 24 for PCS1900. For added baseband interface flexibility, the four-pole filter, its associated Variable Gain Amplifier (VGA), and DC offset correction loop can be bypassed and turned off for current savings. In Table 2 the typical locations of all eight receiver baseband poles are given. The final four poles are produced by the tunable gmC filter, as set by the external resistor (recommended value is 39.2 k Ω, 1%) placed from pin 29 to ground. For these tunable poles, Table 2 gives the pole location as a function of this resistor. DC Offset Correction Three DC offset correction (DCOC) loops ensure that DC offsets, generated in the CX74063-3x, do not overload the baseband chain at any point. After compensation, the correction voltages are held on capacitors for the duration of the receive slot(s). Internally, on-chip timing is provided to generate the track and hold (T_H) signals for the three correction loops. The timing diagram for the DC offset correction sequence with reference to the receive slot is shown in Figure 4. A rising edge on either the RXENA signal, selected via the serial interface, places the DC compensation circuitry in the track mode. The timing parameters for each of the three compensation loops, tt_H1, tt_H2, and tt_H3, and the time between compensation start and the LNA being turned on, tFEENA, are defined via an internal state machine. The state machine is preprogrammed with fixed default values, but may be readjusted via the serial interface. The timing parameters for the three compensation loops and the LNA power-up are each independently defined, relative to the compensation start. Therefore, they may be programmed to occur in any order, but the sequences shown in Figure 4 and Figure 5 are recommended. The device default timing is shown in Figure 5, with a total time of 60 μs. Individual default timings are given in Table 17. For user-programmed timing, the total time may be set as short as approximately 10 μs when FREF has a 13 MHz clock applied. However, the shortest recommended total time is approximately 30 μs, since at the highest gain settings, the resulting DC may degrade as correction time is reduced. AM Suppression and IP2 Calibration For direct conversion GSM applications, it is imperative to have extremely low second-order distortion. Mathematically, second-order distortion of a constant tone generates a DC- term proportional to the square of the amplitude. A strong interfering amplitude-modulated (AM) signal is therefore demodulated by second-order distortion in the receiver front end, and generates an interfering baseband signal. Table 2. Receive Pole Locations Stage Typical Pole Location (rad/sec) Pole Type –1.0 x 106 Real (capacitors at pins 25-26 and 27-28 fixed at 470 pF) Mixer + RC Filter –1.65 x 106 Real LPF1 (–0.91 x 106) ± j(1.35 x 106) Conjugate (–0.91 x 106) x (39.2 k Ω/R) Real (adjust with resistor at pin 29) (–0.91 x 106) x (39.2 k Ω/R) Real (adjust with resistor at pin 29) VGA1 + gmC filter [(–0.46 x 106) ± j(1.0 x 106)] x (39.2 kΩ/R) Conjugate (adjust with resistor at pin 29) |
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