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74AUP1G57 Datasheet(PDF) 5 Page - NXP Semiconductors |
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74AUP1G57 Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 22 page 74AUP1G57_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 — 16 January 2006 5 of 22 Philips Semiconductors 74AUP1G57 Low power configurable multiple function gate Fig 5. 2-input AND gate or 2-input NOR gate with both inputs inverted Fig 6. 2-input NAND gate with input B inverted or 2-input OR gate with inverted C input Fig 7. 2-input NAND gate with input C inverted or 2-input OR gate with inverted A input Fig 8. 2-input NOR gate or 2-input AND gate with both inputs inverted Fig 9. 2-input XNOR gate Fig 10. Inverter Fig 11. Buffer 001aab584 B B6 Y C 1 5 2 4 3Y Y C B C VCC 001aab585 B B6 Y C 1 5 2 4 3Y Y C B C VCC 001aab586 A A 6 Y C 1 5 2 4 3Y Y C A C VCC 001aab587 A 6C 1 5 2 4 3Y VCC A Y C Y A C 001aab588 B6 C 1 5 2 4 3Y VCC Y B C 001aab589 A A 6 Y 1 5 2 4 3Y VCC 001aab590 B B6 Y 1 5 2 4 3Y VCC |
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