Quad DMOS Full Bridge PWM Motor Driver

A3988

5

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Functional Description

stepper motors, four dc motors, or one stepper and two dc motors.

The currents in each of the output full-bridges, all N-channel

DMOS, are regulated with fixed off-time pulse width modulated

(PWM) control circuitry. Each full-bridge peak current is set by

a high value pull-up resistor in order to limit current to the logic

inputs, should an overvoltage event occur. Logic inputs include:

PHASEx, I0x, and I1x.

trolled by a fixed off-time PWM current control circuit that limits

of source and sink DMOS outputs are enabled and current flows

current sense resistor equals the voltage on the VREFx pin, the

current sense comparator resets the PWM latch, which turns off

the source driver.

The maximum value of current limiting is set by the selection of

function approximated by:

Each current step is a percentage of the maximum current,

Note: It is critical to ensure that the maximum rating of

±500 mV

on each SENSEx pin is not exceeded.

uses a one shot circuit to control the time the drivers remain off.

comparator when the outputs are switched by the internal current

control circuitry. The comparator output is blanked to prevent

false detections of overcurrent conditions, due to reverse recovery

currents of the clamp diodes, or to switching transients related to

approximately 1

μs.

try standard I1, I0, and PHASE interface. This communication

logic allows for full, half, and quarter step modes. Each bridge

modes can be programmed by dynamically changing the voltage

on the VREFx pins.

source-side DMOS gates. A 0.1

μF ceramic capacitor should be

connected between CP1 and CP2 for pumping purposes. A 0.1

μF

ceramic capacitor is required between VCP and VBBx to act as a

reservoir to operate the high-side DMOS devices.

perature, or low voltage on VCP), the outputs of the device are

disabled until the fault condition is removed. At power-up, the

undervoltage lockout (UVLO) circuit disables the drivers.

Functional Description