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EP20K400E Datasheet(PDF) 72 Page - Altera Corporation |
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EP20K400E Datasheet(HTML) 72 Page - Altera Corporation |
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72 / 117 page  72 Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Figure 40. Synchronous Bidirectional Pin External Timing Notes to Figure 40: (1) The output enable and input registers are LE registers in the LAB adjacent to a bidirectional row pin. The output enable register is set with “Output Enable Routing= Signal-Pin” option in the Quartus II software. (2) The LAB adjacent input register is set with “Decrease Input Delay to Internal Cells= Off”. This maintains a zero hold time for lab adjacent registers while giving a fast, position independent setup time. A faster setup time with zero hold time is possible by setting “Decrease Input Delay to Internal Cells= ON” and moving the input register farther away from the bidirectional pin. The exact position where zero hold occurs with the minimum setup time, varies with device density and speed grade. Table 31 describes the fMAX timing parameters shown in Figure 36 on page 68. PRN CLRN DQ PRN CLRN DQ (1) IOE Register Bidirectional Pin Dedicated Clock PRN CLRN DQ (1) XZBIDIR t ZXBIDIR t OUTCOBIDIR t INSUBIDIR t INHBIDIR t OE Register Output IOE Register Input Register (2) Table 31. APEX 20K fMAX Timing Parameters (Part 1 of 2) Symbol Parameter tSU LE register setup time before clock tH LE register hold time after clock tCO LE register clock-to-output delay tLUT LUT delay for data-in tESBRC ESB Asynchronous read cycle time tESBWC ESB Asynchronous write cycle time tESBWESU ESB WE setup time before clock when using input register tESBDATASU ESB data setup time before clock when using input register tESBDATAH ESB data hold time after clock when using input register tESBADDRSU ESB address setup time before clock when using input registers tESBDATACO1 ESB clock-to-output delay when using output registers |
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