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EP20K400E Datasheet(PDF) 74 Page - Altera Corporation |
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EP20K400E Datasheet(HTML) 74 Page - Altera Corporation |
74 / 117 page 74 Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Note to Tables 32 and 33: (1) These timing parameters are sample-tested only. Tables 34 through 37 show APEX 20KE LE, ESB, routing, and functional timing microparameters for the fMAX timing model. Table 34. APEX 20KE LE Timing Microparameters Symbol Parameter tSU LE register setup time before clock tH LE register hold time after clock tCO LE register clock-to-output delay tLUT LUT delay for data-in to data-out Table 35. APEX 20KE ESB Timing Microparameters Symbol Parameter tESBARC ESB Asynchronous read cycle time tESBSRC ESB Synchronous read cycle time tESBAWC ESB Asynchronous write cycle time tESBSWC ESB Synchronous write cycle time tESBWASU ESB write address setup time with respect to WE tESBWAH ESB write address hold time with respect to WE tESBWDSU ESB data setup time with respect to WE tESBWDH ESB data hold time with respect to WE tESBRASU ESB read address setup time with respect to RE tESBRAH ESB read address hold time with respect to RE tESBWESU ESB WE setup time before clock when using input register tESBWEH ESB WE hold time after clock when using input register tESBDATASU ESB data setup time before clock when using input register tESBDATAH ESB data hold time after clock when using input register tESBWADDRSU ESB write address setup time before clock when using input registers tESBRADDRSU ESB read address setup time before clock when using input registers tESBDATACO1 ESB clock-to-output delay when using output registers tESBDATACO2 ESB clock-to-output delay without output registers tESBDD ESB data-in to data-out delay for RAM mode tPD ESB Macrocell input to non-registered output tPTERMSU ESB Macrocell register setup time before clock tPTERMCO ESB Macrocell register clock-to-output delay |
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