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HD-15530-8 Datasheet(PDF) 3 Page - Intersil Corporation |
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HD-15530-8 Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 13 page 144 Encoder Operation The Encoder requires a single clock with a frequency of twice the desired data rate applied at the SEND CLOCK input. An auxiliary divide by six counter is provided on chip which can be utilized to produce the SEND CLOCK by divid- ing the DECODER CLOCK. The Encoder’s cycle begins when ENCODER ENABLE is high during a falling edge of ENCODER SHIFT CLOCK . This cycle lasts for one word length or twenty ENCODER SHIFT CLOCK periods. At the next low-to-high transition of the ENCODER SHIFT CLOCK, a high SYNC SELECT input actuates a command sync or a low will produce a data sync for the word . When the Encoder is ready to accept data, the SEND DATA output will go high and remain high for six- teen ENCODER SHIFT CLOCK periods . During these sixteen periods the data should be clocked into the SERIAL DATA input with every high-to-low transition of the ENCODER SHIFT CLOCK so it can be sampled on the low- to-high transition - . After the sync and Manchester II coded data are transmitted through the BIPOLAR ONE and BIPOLAR ZERO outputs, the Encoder adds on an additional bit which is the parity for that word . If ENCODER ENABLE is held high continuously, consecutive words will be encoded without an interframe gap. ENCODER ENABLE must go low by time as shown to prevent a consecutive word from being encoded. At any time a low on OUTPUT INHIBIT input will force both bipolar outputs to a high state but will not affect the Encoder in any other way. To abort the Encoder transmission a positive pulse must be applied at MASTER RESET. Anytime after or during this pulse, a low-to-high transition on SEND CLOCK clears the internal counters and initializes the Encoder for a new word. 18 I SERIAL DATA IN Encoder Accepts a serial data stream at a data rate equal to ENCODER SHIFT CLOCK. 19 I ENCODER ENABLE Encoder A high on this pin initiates the encode cycle. (Subject to the preceeding cycle being complete.) 20 I SYNC SELECT Encoder Actuates a Command sync for an input high and Data sync for an input low. 21 O SEND DATA Encoder An active high output which enables the external source of serial data. 22 I SEND CLOCK IN Encoder Clock input at a frequency equal to the data rate X2, usually driven by ÷ 6 output. 23 I ENCODER CLOCK Encoder Input to the 6:1 divider, a frequency equal to the data rate X12 is usually input here. 24 I VCC Both VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (pin 24) to GROUND (pin 12) is recommended. I = Input O = Output Pin Description (Continued) PIN NUMBER TYPE NAME SECTION DESCRIPTION 1 2 3 3 4 5 5 FIGURE 1. DON’T CARE VALID DON’T CARE P 0 1 2 3 P 0 1 2 3 0 1 2 3 19 15 16 17 18 7 6 5 4 11 12 13 14 15 11 12 13 14 15 11 12 13 14 15 10 SYNC SYNC 2ND HALF 1ST HALF 3 2 1 0 TIMING SEND CLK ENCODER SHIFT CLK ENCODER SYNC SELECT SEND DATA SERIAL BIPOLAR ONE OUT BIPOLAR ZERO OUT 1 2 3 4 5 ENABLE DATA IN HD-15530 |
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