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SN74LVC138APWE4 Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LVC138APWE4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 24 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) GQN OR ZQN PACKAGE (TOP VIEW) 1 2 3 4 A B C D E SN54LVC138A, SN74LVC138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCAS291T – MARCH 1993 – REVISED JULY 2005 The 'LVC138A devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. TERMINAL ASSIGNMENTS 1 2 3 4 A B A VCC Y0 B C NC(1) NC(1) Y1 C G2B G2A Y3 Y2 D G1 NC(1) NC(1) Y4 E GND Y7 Y6 Y5 (1) NC - No internal connection SDFGDFGDFG FUNCTION TABLE ENABLE INPUTS SELECT INPUTS OUTPUTS G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X H X X X X H H H H H H H H X X H X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L 2 |
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