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TPS72525KTTTG3 Datasheet(PDF) 6 Page - Texas Instruments |
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TPS72525KTTTG3 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 22 page www.ti.com NOTES:A. VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards for semiconductor symbology. IN VRES (see Note A) VRES t t t OUT Threshold Voltage RESET Output 50 ms Delay 50 ms Delay Output Undefined Output Undefined VIT+(see Note B) VIT– (see Note B) VIT+(see Note B) B. VIT –Trip voltage is typically 7% lower than the output voltage (93%VO) VIT– to VIT+ is the hysteresis voltage. VIT– (see Note B) TPS72501 TPS72515, TPS72516 TPS72518, TPS72525 SLVS341D – MAY 2002 – REVISED MARCH 2004 RESET TIMING DIAGRAM 6 |
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