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SN74GTL16616DLRG4 Datasheet(PDF) 6 Page - Texas Instruments |
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SN74GTL16616DLRG4 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 14 page  www.ti.com Timing Requirements SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCBS481H – JUNE 1994 – REVISED APRIL 2005 over recommended ranges of supply voltage and operating free-air temperature, V TT = 1.2 V and VREF = 0.8 V for GTL (unless otherwise noted) (see Figure 1) MIN MAX UNIT fclock Clock frequency 95 MHz LEAB or LEBA high 3.3 tw Pulse duration ns CLKAB or CLKBA high or low 5.5 A before CLKAB ↑ 1.3 B before CLKBA ↑ 2.5 A before LEAB ↓ 0 tsu Setup time ns B before LEBA ↓ 1.1 CEAB before CLKAB ↑ 2.2 CEBA before CLKBA ↑ 2.7 A after CLKAB ↑ 1.6 B after CLKBA ↑ 0.4 A after LEAB ↓ 4 th Hold time ns B after LEBA ↓ 3.5 CEAB after CLKAB ↑ 1.1 CEBA after CLKBA ↑ 0.9 6 |
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