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MC100E136FNR2 Datasheet(PDF) 1 Page - ON Semiconductor |
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MC100E136FNR2 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 12 page © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 9 1 Publication Order Number: MC10E136/D MC10E136, MC100E136 5VECL 6-Bit Universal Up/Down Counter Description The MC10E/100E136 is a 6-bit synchronous, presettable, cascadable universal counter. The device generates a look-ahead-carry output and accepts a look-ahead-carry input. These two features allow for the cascading of multiple E136’s for wider bit width counters that operate at very nearly the same frequency as the stand alone counter. The CLOUT output will pulse LOW for one clock cycle one count before the E136 reaches terminal count. The COUT output will pulse LOW for one clock cycle when the counter reaches terminal count. For more information on utilizing the look-ahead-carry features of the device please refer to the applications section of this data sheet. The differential COUT output facilitates the E136’s use in programmable divider and self-stopping counter applications. Unlike the H136 and other similar universal counter designs, the E136 carry−out and look-ahead-carry−out signals are registered on chip. This design alleviates the glitch problem seen on many counters where the carry out signals are merely gated. Because of this architecture there are some minor functional differences between the E136 and H136 counters. The user, regardless of familiarity with the H136, should read this data sheet carefully. Note specifically (see logic diagram) the operation of the carry out outputs and the look-ahead-carry in input when utilizing the master reset. When left open all of the input pins will be pulled LOW via an input pull−down resistor. The master reset is an asynchronous signal which when asserted will force the Q outputs LOW. The Q outputs need not be terminated for the E136 to function properly, in fact if these outputs will not be used in a system it is recommended to save power and minimize noise that they be left open. This practice will minimize switching noise which can reduce the maximum count frequency of the device or significantly reduce margins against other noise in the system. The 100 Series contains temperature compensation. Features • 550 MHz Count Frequency • Fully Synchronous Up and Down Counting • Look-Ahead-Carry Input and Output • Asynchronous Master Reset • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V • Internal Input 50 kW Pulldown Resistors • ESD Protection: Human Body Model: > 2 kV, Machine Model: > 200 V • Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test • Moisture Sensitivity Level: Pb = 1; Pb−Free = 3 For Additional Information, see Application Note AND8003/D • Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 • Transistor Count = 506 devices • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. MARKING DIAGRAM* xxx = 10 or 100 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package PLCC−28 FN SUFFIX CASE 776 MCxxxE136G AWLYYWW 1 http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ORDERING INFORMATION |
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