TLC876M, TLC876I, TLC876C

10-BIT 20 MSPS PARALLEL OUTPUT CMOS

ANALOG-TO-DIGITAL CONVERTERS

SLAS140E – JULY 1997 – REVISED OCTOBER 2000

7

POST OFFICE BOX 655303

dc accuracy

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Integral nonlinearity (INL)

±1.5

LSB

Differential nonlinearity (DNL) (see Note 1)

±0.5

<±1

LSB

Offset error

–0.4

%FSR

Gain error

0.2

%FSR

NOTE 1: A differential nonlinearity error of less than

±1 LSB ensures no missing codes.

analog input

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Ci

Input capacitance

5

pF

reference input

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Rref

Reference input resistance

350

500

Ω

Iref

Reference input current

4

mA

Reference top offset voltage

35

mV

Reference bottom offset voltage

35

mV

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

All suffixes

fI = 1 MHz

8.5

Eff

ti

b

f bit (ENOB)

All suffixes

fI = 3.58 MHz,

TA = 25°C

8

8.5

Bit

Effective number of bits (ENOB)

C and I suffixes

fI = 3.58 MHz,

8

8.5

Bits

M suffix

I

,

TA = Full Range

7.5

All suffixes

fI = 10 MHz

8.1

All suffixes

fI = 1 MHz

53

Signal-to-total harmonic distortion+noise

All suffixes

fI = 3.58 MHz,

TA = 25°C

50

53

dB

Signal to total harmonic distortion+noise

(S/(THD+N))

C and I suffixes

fI = 3.58 MHz,

50

53

dB

M suffix

I

,

TA = Full Range

47

All suffixes

fI = 10 MHz

51

fI = 1 MHz

–63

Total harmonic distortion (THD)

fI = 3.58 MHz

–62

–56

dB

fI = 10 MHz

–61

Spurious free dynamic range

fI = 3.58 MHz

–64

dB

BW

Analog input full-power bandwidth

200

MHz

Differential phase

0.5

degrees

Differential gain

1%

† The voltage difference between AVDD and DVDD cannot exceed 0.5 V to maintain performance specifications. At input clock rise times less than

20 ns, the offset full-scale error increases approximately by a factor of (20/tr)0.5 where tr equals the actual rise time in nanoseconds.