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MC100EP32DR2 Datasheet(PDF) 2 Page - ON Semiconductor

Part No. MC100EP32DR2
Description  3.3V / 5V ECL ÷2 Divider
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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 2 page
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MC10EP32, MC100EP32
http://onsemi.com
2
1
2
3
45
6
7
8
Q
VEE
VCC
Figure 1. 8−Lead Pinout (Top View) and Logic
Diagram
CLK
Q
CLK
VBB
RESET
R
B2
Table 1. PIN DESCRIPTION
Pin
Function
CLK, CLK*
ECL Clock Inputs
Reset*
ECL Asynchronous Reset
VBB
Reference Voltage Output
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
EP
Exposed pad must be connected to a
sufficient thermal conduit. Electrically
connect to the most negative supply or
leave floating open.
*Pins will default LOW when left open.
Table 2. TRUTH TABLE
CLK
CLK
RESET
Q
Q
X
Z
X
Z
Z
L
L
F
H
F
Z = LOW to HIGH Transition
Z = HIGH to LOW Transition
F = Divide by 2 Function
Figure 2. Timing Diagram
CLK
RESET
Q
tRR
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
SOIC−8
TSSOP−8
DFN8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
78 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.




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