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MC100EP51MNR4G Datasheet(PDF) 6 Page - ON Semiconductor

Part No. MC100EP51MNR4G
Description  3.3V / 5V ECL D Flip−Flop with Reset and Differential Clock
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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 6 page
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MC10EP51, MC100EP51
http://onsemi.com
6
Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 17)
Symbol
Characteristic
−40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
IEE
Power Supply Current
26
34
44
26
35
45
28
37
47
mA
VOH
Output HIGH Voltage (Note 18)
−1145 −1020
−895
−1145 −1020
−895
−1145 −1020
−895
mV
VOL
Output LOW Voltage (Note 18)
−1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695
mV
VIH
Input HIGH Voltage (Single−Ended)
−1225
−880
−1225
−880
−1225
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1945
−1625 −1945
−1625 −1945
−1625
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
VEE + 2.0
0.0
VEE + 2.0
0.0
VEE + 2.0
0.0
V
IIH
Input HIGH Current
150
150
150
mA
IIL
Input LOW Current
0.5
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17.Input and output parameters vary 1:1 with VCC.
18.All loading with 50 W to VCC − 2.0 V.
19.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20)
Symbol
Characteristic
−40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Frequency (Figure 2)
> 3
> 3
> 3
GHz
tPLH,
tPHL
Propagation Delay to Output Differential
CLK, CLK to Q, Q
10
100
RESET to Q, Q
250
275
300
300
340
380
350
425
450
270
300
325
320
375
400
370
450
475
300
350
350
350
425
425
420
500
500
ps
tRR
Reset Recovery
150
150
150
ps
tS
tH
Setup Time
Hold Time
100
100
100
100
80
40
100
100
ps
tPW
Minimum Pulse Width
RESET
500
440
500
440
500
440
ps
tJITTER
Cycle−to−Cycle Jitter (Figure 2)
.2
< 1
.2
< 1
.2
< 1
ps
tr
tf
Output Rise/Fall Times
Q, Q
(20% − 80%)
70
120
170
80
130
180
100
150
200
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.




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