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MC100H642FNR2 Datasheet(PDF) 5 Page - ON Semiconductor |
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MC100H642FNR2 Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 10 page MC10H642, MC100H642 http://onsemi.com 5 Figure 3. MC10H642 Positive PW versus Load @ ±5% VCC, TA = 25°C 5.25 5.00 4.75 11 10 9 0 1020 304050 60 CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) Figure 4. MC10H642 Negative PW versus Load @ ±5% VCC, TA = 25°C 5.25 5.00 4.75 11 10 9 0 10 20 304050 60 CAPACITIVE LOAD (pF) Figure 5. MC10H642 Positive PW versus Load @ ±2.5% VCC, TA = 25°C 5.125 5.00 4.875 10.6 10.4 10.2 10.0 9.8 9.6 9.4 9.2 0 10 203040 5060 CAPACITIVE LOAD (pF) Figure 6. MC10H642 Negative PW versus Load @ ±2.5% VCC, TA = 25°C 5.125 5.00 4.875 10.8 10.6 10.4 10.2 10.0 9.8 9.6 9.4 0 10 2030 4050 60 TEMPERATURE (°C) Figure 7. MC10H642 Positive PW versus Temperature, VCC = 5.0 V 50 pF 25 pF 0 pF 10.4 10.2 10.0 9.8 9.6 9.4 0 2040 6080 100 Figure 8. MC10H642 Negative PW versus Temperature, VCC = 5.0 V 50 pF 25 pF 0 pF 10.5 10.3 10.1 9.9 9.7 9.5 0 20 40 60 80 100 TEMPERATURE (°C) 10/100H642 − DUTY CYCLE CONTROL To maintain a duty cycle of ±5% at 50 MHz, limit the load capacitance and/or power supply variation as shown in Figures 1 and 2. For a ±2.5% duty cycle limit, see Figures 3 and 4. Figures 5 and 6 show duty cycle variation with temperature. Figure 7 shows typical TPD versus load. Figure 8 shows reset recovery time. Figure 9 shows output states after power up. Best duty cycle control is obtained with a single mP load and minimum line length. |
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