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MV1820 Datasheet(PDF) 3 Page - Zarlink Semiconductor Inc

Part No. MV1820
Description  Video Programme Delivery Control Interface Circuit
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MV1820 Datasheet(HTML) 3 Page - Zarlink Semiconductor Inc

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MV1820
4
CRYSTAL SPECIFICATION
Parallel resonant fundamental frequency 27.750000MHz. AT cut.
Nominal load capacitance 20pF.
Tolerance at -10
°C to 60°C ± 50ppm.
Equivalent series resistance <20
Ω.
Tolerance overall
± 100ppm.
FUNCTIONAL DESCRIPTION
The video signal is sliced to produce data and
synchronising signals. Timing circuits monitor the sync signal
to enable the MV1820 to lock onto the broadcast signal. A
timing window, for the Vertical Blanking Interval (VBI) lines 6
- 22 and 318 - 335, is established to enable the acquisition
circuit to monitor the sliced data signal for valid teletext data.
The framing code is checked for valid World System
Teletext (WST) data. Magazine, packet and designation code
bytes are checked and valid Broadcast Service Data Packets
(BSDP) format two type only are accepted. These are known
as packet 8/30. Format two is signalled by byte six, data bit two
being set high and bits 3 and 4 set low. Bytes 13 to 25 inclusive
are Hamming decoded (8,4) and stored in seven registers
each of eight bits. If the complete message is correctly
received with no uncorrectable Hamming errors, an interrupt
to the microprocessor is signalled by the DAV (bar) pin going
low. At the same time the data is transferred to a second bank
of registers, reorganised with original numbered bytes 14, 15,
24, 25 and 13 placed after byte 23, to be read out on the I2C
bus when so requested. Subsequent valid messages will
continue to be transferred to the output registers overwriting
any existing data. In this way the output registers always
contain the latest PDC message.
The MV1820 is configured as an I2C bus slave transmitter
with a selectable address. The I2C bus address is 0010 0001
(20 + 1 hex) with the address select (AS) pin set high, or 0010
0011 (22 + 1 hex) with the AS pin set low. The read bit (LSB)
must always be set, it is not possible to write to the MV1820.
On recognising its address, the MV1820 will send an
acknowledge and then transmit on the SDA line the first byte
from the output registers (decoded byte 16 and 17) most
significant bit (MSB) first. It will then monitor the SDA line for
an acknowledge from the microprocessor. If the
microprocessor does NOT send an acknowledge, the
MV1820 will release the data line to allow the microprocessor
to send a stop condition. If the microprocessor does send an
acknowledge, the following bytes of the message will be
output provided each byte is acknowledged. The final data will
be byte 13 followed by the four ‘1’s.
When readout is complete, the DAV (bar) pin is reset high
and the output registers are all set high. If the microprocessor
continues to send clocks on the SCL line, the MV1820 will
output FF bytes on the SDA line. Also, if the MV1820 is re-
addressed before another PDC message is received, the
MV1820 will output FF bytes on the SDA line. The
microprocessor can prematurely stop the message by NOT
sending an Acknowledge followed by a STOP condition after
any byte has been sent by the MV1820. The registers will then
be reset to FF bytes and the DAV pin will be reset high.
To prevent any corruption of the data in the output
registers during I2C bus activity, valid PDC messages are held
in the incoming registers until I2C bus activity ceases. Here
they may be overwritten by new PDC messages until the I2C
bus activity ceases and they can then be transferred to the
output registers.
System clock is provided by an on - chip 27.75MHz
oscillator together with an external parallel resonant
fundamental frequency AT cut crystal.
Following a reset, RESET pulled low, the output I2C bus
registers will contain FF bytes and the DAV pin will be set high.
When the power supply is removed, the I2C bus will not be
clamped to ground, leaving it free for other I2C bus traffic.
Fig.3 Typical application diagram


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