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SP8402MPES Datasheet(PDF) 1 Page - Zarlink Semiconductor Inc |
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SP8402MPES Datasheet(HTML) 1 Page - Zarlink Semiconductor Inc |
1 / 6 page SP8402 Very Low Phase Noise Divider by 2N September 2005 The SP8402 is a very low phase noise divider which divides by powers of two. The S0, S1, S2 data inputs select the division ratio in the range 21 to 28. Special circuits techniques have been used to reduce the phase noise considerably below that produced by standard dividers. The data inputs are CMOS or TTL compatible. The SP8402 is packaged in a 28 pin plastic SO package to be compatible with the SP8400 and SP8401 devices. FEATURES I Very low Phase Noise (Typically -155 to 160dBc/Hz at 1kHz offset) I Supply Voltage 5V ABSOLUTE MAXIMUM RATINGS Supply Voltage 6.5V Output Current 20mA Storage Temperature Range -55 °C to +125°C Maximum Clock Input Voltage 2.5V p-p MP28 Fig.1 Pin connections - top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 N/C N/C N/C VCC +5V GND CLOCK INPUT CLOCK INPUT CLOCK INPUT GND VCC +5V VCC +5V N/C S0 N/C N/C N/C N/C N/C N/C N/C OUTPUT OUTPUT N/C VCC +5V N/C S2 S1 CLOCK INPUT Fig.2 Typical single sideband phase noise measured at 768MHz Frequency (Hz) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k 100k Ordering Information SP8402/KG/MPES 28 Pin SOIC Tubes SP8402/KG/MPFP 28 Pin SOIC* Tubes SP8402/KG/MP1T 28 Pin SOIC Tape & Reel *Pb Free Matte Tin 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1994-2005, Zarlink Semiconductor Inc. All Rights Reserved. |
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