MC74HC164A

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6

PIN DESCRIPTIONS

INPUTS

A1, A2 (Pins 1, 2)

Serial Data Inputs. Data at these inputs determine the data

to be entered into the first stage of the shift register. For a

high level to be entered into the shift register, both A1 and

A2 inputs must be high, thereby allowing one input to be

used as a data−enable input. When only one serial input is

Clock (Pin 8)

Shift Register Clock. A positive−going transition on this

pin shifts the data at each stage to the next stage. The shift

register is completely static, allowing clock rates down to

DC in a continuous or intermittent mode.

OUTPUTS

Parallel Shift Register Outputs. The shifted data is

presented at these outputs in true, or noninverted, form.

CONTROL INPUT

Reset (Pin 9)

Active−Low, Asynchronous Reset Input. A low voltage

applied to this input resets all internal flip−flops and sets

SWITCHING WAVEFORMS

GND

90%

50%

10%

CLOCK

Q

Figure 1.

RESET

Figure 2.

90%

50%

10%

GND

GND

Q

CLOCK

50%

50%

50%

A1 OR A2

Figure 3.

GND

GND

50%

50%

CLOCK

VALID

*Includes all probe and jig capacitance

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 4. Test Circuit