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MC74HC165ADR2 Datasheet(PDF) 5 Page - ON Semiconductor |
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MC74HC165ADR2 Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 12 page MC74HC165A http://onsemi.com 5 TIMING REQUIREMENTS (Input tr = tf = 6 ns) Symbol Parameter VCC V Guaranteed Limit Unit – 55 to 25 _C v 85_C v 125_C tsu Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load (Figure 4) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns tsu Minimum Setup Time, Input SA to Clock (or Clock Inhibit) (Figure 5) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns tsu Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit) (Figure 6) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns tsu Minimum Setup Time, Clock to Clock Inhibit (Figure 7) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns th Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs (Figure 4) 2.0 3.0 4.5 6.0 5 5 5 5 5 5 5 5 5 5 5 5 ns th Minimum Hold Time, Clock (or Clock Inhibit) to Input SA (Figure 5) 2.0 3.0 4.5 6.0 5 5 5 5 5 5 5 5 5 5 5 5 ns th Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load (Figure 6) 2.0 3.0 4.5 6.0 5 5 5 5 5 5 5 5 5 5 5 5 ns trec Minimum Recovery Time, Clock to Clock Inhibit (Figure 7) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns tw Minimum Pulse Width, Clock (or Clock Inhibit) (Figure 1) 2.0 3.0 4.5 6.0 70 27 15 13 90 32 19 16 100 36 22 19 ns tw Minimum Pulse width, Serial Shift/Parallel Load (Figure 2) 2.0 3.0 4.5 6.0 70 27 15 13 90 32 19 16 100 36 22 19 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). |
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