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A3950 Datasheet(PDF) 3 Page - Allegro MicroSystems |
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A3950 Datasheet(HTML) 3 Page - Allegro MicroSystems |
3 / 12 page DMOS Full-Bridge Motor Driver A3950 3 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com UVLO STB STG TSD Warning VBB OUTA OUTB SENSE Low-Side Gate Supply Charge Pump Motor Lead Protection Pad Control Logic Bias Supply GND GND SLEEP NFAULT PHASE ENABLE VDD 5 kΩ 5 kΩ MODE VREG 0.22 μF 25 V 0.1 μF 0.1 μF 0.1 μF 100 μF OUTA VBB VCP Load Supply CP2 CP1 OUTB SENSE Functional Block Diagram Terminal List Table Name Number Description EU LP NFAULT 15 1 Fault output, open drain MODE 16 2 Logic input PHASE 1 3 Logic input for direction control GND 2, 12 4,13 Ground SLEEP 3 5 Logic input ENABLE 4 6 Logic input OUTA 6 7 DMOS full-bridge output A SENSE 7 8 Power return VBB 8 9 Load supply voltage OUTB 9 10 DMOS full-bridge output B CP1 10 11 Charge pump capacitor terminal CP2 11 12 Charge pump capacitor terminal VCP 13 14 Reservoir capacitor terminal VREG 14 15 Regulator decoupling terminal NC 5 16 No connection Pad – – Exposed pad for thermal dissipation connect to GND pins |
Similar Part No. - A3950_06 |
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Similar Description - A3950_06 |
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