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2

Connection Diagram

Pin Descriptions

Truth Table

H

= Logic HIGH

L

= Logic LOW

X

= Don’t Care, but not floating

Z

= High Impedance

↑ = LOW-to-HIGH Clock Transition

Note 2: Output level before the indicated steady-state input conditions

were established provided that CLK was HIGH before LE went LOW.

Note 3: Output level before the indicated steady-state input conditions

were established.

Logic Diagram

Pin Names

Description

OE

Output Enable Input (Active LOW)

LE

Latch Enable Input

CLK

Clock Input

Data Inputs

3-STATE Outputs

Inputs

Outputs

OE

LE

CLK

H

XXX

Z

LH

X

L

L

LH

X

H

H

LL

↑

LL

LL

↑

HH

LL

H

X

LLL

X