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TMS320F206 Datasheet(PDF) 7 Page - Texas Instruments |
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TMS320F206 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 58 page  TMS320F206 DIGITAL SIGNAL PROCESSOR SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998 7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram of the ’F206 internal hardware TCR Timer 32 16 Data Bus 16 16 OSCALE (0–7) D15–D0 A15–A0 16 16 16 32 32 ACCL(16) ACCH(16) C 32 CALU(32) 32 32 MUX ISCALE (0–16) 16 MUX PREG(32) Multiplier TREG0(16) MUX 16 16 16 MUX B1 (256 × 16) B2 (32 × 16) DARAM B0 (256 × 16) DARAM MUX 7 LSB from IR MUX DP(9) 9 9 MUX 16 SARAM 16 ARAU(16) 16 MUX 3 3 3 3 ARB(3) ARP(3) Program Bus 16 16 16 16 AR7(16) AR6(16) AR5(16) AR3(16) AR2(16) AR1(16) AR0(16) Stack 8 × 16 PC MUX NMI WE RD 16 CLKIN/X2 CLKOUT1 X1 3 INT[1–3] MP/MC RS HOLDA† HOLD† XF BR READY STRB R/W PS DS IS DIV2 DIV1 AR4(16) 16 Data/Prog Data/Prog 16 PSCALE (–6, 0, 1, 4) 16 Data 32 16 16 16 16 16 FLASH EEPROM (32K × 16) MUX MUX NPAR PAR MSTACK Program Control (PCTRL) PRD TIM ADTR ASP SSPCR SSP SDTR 4 TOUT TX RX I/O[0–3] DX CLKX FSX DR FSR CLKR BRD IOSR Reserved Memory Map Register IMR (16) IFR (16) GREG (16) 16 I/O-Mapped Registers (4K × 16) NOTES: A. Symbol descriptions appear in Table 3. B. For clarity the data and program buses are shown as single buses although they include address and data bits. |
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