IS61LV12816

Integrated Silicon Solution, Inc. — 1-800-379-4774

5

Rev. C

02/05/2003

-10 ns

-12 ns

-15 ns

Symbol Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Read Cycle Time

10

—

12

—

15

—

ns

Address Access Time

—

10

—

12

—

15

ns

Output Hold Time

3

—

3

—

3

—

ns

CE Access Time

—

10

—

12

—

15

ns

OE Access Time

—

4

—

5

—

6

ns

OE to High-Z Output

—

4

—

5

0

6

ns

OE to Low-Z Output

0

—

0

—

0

—

ns

CE to High-Z Output

0

4

0

5

0

8

ns

CE to Low-Z Output

3

—

3

—

3

—

ns

LB, UB Access Time

—

4

—

5

—

6

ns

LB, UB to High-Z Output

0

4

0

5

0

6

ns

LB, UB to Low-Z Output

0

—

0

—

0

—

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input

pulse levels of 0V to 3.0V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not

100% tested.

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

6

pF

Input/Output Capacitance

8

pF

Note:

1. Tested initially and after any design or process changes that may affect these parameters.