Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. C

02/05/2003

IS61LV12816

Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice.

ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

FEATURES

• High-speed access time: 10, 12, and 15 ns

• CMOS low power operation

• TTL and CMOS compatible interface levels

• Single 3.3V ± 10% power supply

• Fully static operation: no clock or refresh

required

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

128K x 16 HIGH-SPEED CMOS STATIC RAM

WITH 3.3V SUPPLY

DESCRIPTION

The

RAM organized as 131,072 words by 16 bits. It is fabricated

using

highly reliable process coupled with innovative circuit design

techniques, yields access times as fast as 10 ns with low

power consumption.

When

CE is HIGH (deselected), the device assumes a

standby mode at which the power dissipation can be

reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable

and Output Enable inputs,

CE and OE. The active LOW

Write Enable (

WE) controls both writing and reading of the

memory. A data byte allows Upper Byte (

UB) and Lower

Byte (

LB) access.

The IS61LV12816 is packaged in the JEDEC standard 44-

pin 400-mil SOJ, 44-pin TSOP (Type II), 44-pin LQFP, and

48-pin mini BGA (6mm x 8mm).

FUNCTIONAL BLOCK DIAGRAM

FEBRUARY 2003

A0-A16

CE

OE

WE

128K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB