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SP6133ER1 Datasheet(PDF) 6 Page - Sipex Corporation |
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SP6133ER1 Datasheet(HTML) 6 Page - Sipex Corporation |
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6 / 20 page  6 Oct 24-06 Rev L SP633 Synchronous Buck Controller © 2006 Sipex Corporation THEORY OF OPERATION The SP6133 contains two unique control features that are very powerful in distributed applications. First, non-synchronous driver control is enabled during start up to prohibit the low side NFETfrom pulling down the out- put until the high side NFEThas attempted to turn on. Second, a 00% duty cycle timeout ensuresthatthelowsideNFETisperiodically enhanced during extended periods at 00% dutycycle.Thisguaranteesthesynchronized refreshing of the BST capacitor during very large duty ratios. The SP633 also contains a number of valu- able protection features. A programmable input UVLO allows a user to set the exact value at which the conversion voltage is at a safe point to begin down conversion, and an internalVCCUVLOensuresthatthecontroller itselfhasenoughvoltagetoproperlyoperate. Other protection features include thermal shutdown and short-circuit detection. In the event that either a thermal, short-circuit, or UVLO fault is de- tected,theSP633isforcedintoanidlestate where the output drivers are held off for a finiteperiodbeforeare-startisattempted. Soft Start “Soft Start” is achieved when a power con- verter ramps up the output voltage while controlling the magnitude of the input sup- ply source current. In a modern step down converter,rampingupthenon-invertinginput oftheerroramplifiercontrolssoftstart.Asa result,excesssourcecurrentcanbedefined asthecurrentrequiredtochargetheoutput capacitor IVIN, x = Cout •∆Vout ∆ TSoft-start The SP633 provides the user with the op- tion to program the soft start rate by tying a capacitor from the SS pin to GND. The selection of this capacitor is based on the 0µA pull up current present at the SS pin and the 0.8V reference voltage. Therefore, theexcesscurrentsourcecanberedefinedas: IVIN, x = COUT • ∆VOUT • 0µA (CSS •0.8V) Hiccup Upon the detection of a power, thermal, or short-circuit fault, the SP633 is forced into an idle state for a minimum of 200ms. The SS and COMP pins are immediately pulled low, and the gate drivers are held off for the duration of the timeout period. Power and thermal faults have to be removed before a restart may be attempted, whereas, a short- circuit fault is internally cleared shortly after the fault latch is set. Therefore, a restart at- temptisguaranteedevery200ms(typical)as long as the short-circuit condition persists. A short-circuit detection comparator has also been included in the SP633 to protect against the accidental short or severe build up of current at the output of the power con- verter. This comparator constantly monitors theinputstotheerroramplifier,andifthe VFB pin ever falls more than 250mV (typical) below the voltage reference, a short-circuit fault is set. Because the SS pin overrides the internal 0.8V reference during soft start, the SP633 is capable of detecting short-circuit faults throughout the duration of soft start as well as in regular operation. Error Amplifier & Voltage Loop As stated before, the heart of the SP633 voltage error loop is a high performance, widebandwidthtransconductanceamplifier. Because of the amplifier’s current limited (+00µA)transconductance,therearemany ways to compensate the voltage loop or to control the COMP pin externally. If a simple, singlepole,singlezeroresponseisrequired, then compensation can be as simple as an RC circuit to ground. If a more complex compensationisrequired,thentheamplifier hasenoughbandwidth(45°Cat4MHz) and enough gain (60 dB) to run Type III |
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