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W83194BR-323 Datasheet(PDF) 11 Page - Winbond |
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W83194BR-323 Datasheet(HTML) 11 Page - Winbond |
11 / 18 page STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET - 8 - W83194BR-323W83194BG-323 7.4 Register 3: PCI, 48MHz Clock Register (1 = enable, 0 = Stopped) BIT PIN NO PWD DESCRIPTION 7 22 1 48MHZ 6 23 1 24_48MHz 5 48 1 REF0 4 1 1 REF1 3 Reserved 1 Reserved 2 8 1 PCICLK_F2 1 7 1 PCICLK_F1 0 6 1 PCICLK_F0 7.5 Register 4: 3V66 Control Register (1 = enable, 0 = Stopped) BIT PIN NO PWD DESCRIPTION 7 - 1 Reserved 6 - 1 Reserved 5 - 1 Reserved 4 - 1 Reserved 3 27 1 3V66_3 / 48MHz 2 28 1 3V66_2 1 30 1 3V66_1 0 31 1 3V66_0 7.6 Register 5: Watchdog Control Register BIT NAME PWD DESCRIPTION 7 MULTISEL1 X MULTISEL1 trapping pin data read back 6 EN_WD 0 Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer. Read this bit will return a counting state. If timer continues down count, this bit will return 1. Otherwise, this bit will return 0. 5 WD_TIMEOUT 0 Watchdog Timeout Status. If the watchdog is started and timer down counts to zero, this bit will be set to 1. Clear this bit to logic 0, If set to 1, when the watchdog is restart in the next time. This bit is Read Only. 4 SAF_FREQ [4] 0 3 SAF_FREQ [3] 0 2 SAF_FREQ [2] 0 1 SAF_FREQ [1] 0 0 SAF_FREQ [0] 0 Watchdog safe frequency bits. These bits will be reloaded into FS [4:0], if the watchdog is timeout and enable reload safe frequency bits. |
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