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CAT24C23ZD2I-GT3 Datasheet(PDF) 8 Page - Catalyst Semiconductor |
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CAT24C23ZD2I-GT3 Datasheet(HTML) 8 Page - Catalyst Semiconductor |
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8 / 18 page  CAT24C32 8 Doc. No. 1101, Rev. G © 2007 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice READ OPERATIONS Immediate Read To read data from memory, the Master creates a START condition on the bus and then broadcasts a Slave ad- dress with the R/W dress with the R/ dress with the R/ bit set to ‘1’. The Slave responds with W W ACK and starts shifting out data residing at the current address. After receiving the data, the Master responds with NoACK and terminates the session by creating a STOP condition on the bus (Figure 9). The Slave then returns to Standby mode. Selective Read To read data residing at a specific address, the selected address must first be loaded into the internal address register. This is done by starting a Byte Write sequence, whereby the Master creates a START condition, then broadcasts a Slave address with the R/W bit set to ‘0’ and then sends two address bytes to the Slave. Rather than completing the Byte Write sequence by sending data, the Master then creates a START condition and broadcasts a Slave address with the R/W broadcasts a Slave address with the R/ broadcasts a Slave address with the R/ bit set to ‘1’. W W The Slave responds withACK after every byte sent by the Master and then sends out data residing at the selected address. After receiving the data, the Master responds with NoACK and then terminates the session by creating a STOP condition on the bus (Figure 10). Sequential Read If, after receiving data sent by the Slave, the Master responds withACK, then the Slave will continue transmit- ting until the Master responds with NoACK followed by STOP (Figure 11). During Sequential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. |
Similar Part No. - CAT24C23ZD2I-GT3 |
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