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MC100EPT24DTG Datasheet(HTML) 4 Page - ON Semiconductor

Part No. MC100EPT24DTG
Description  3.3V LVTTL/LVCMOS to Differential LVECL Translator
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC100EPT24DTG Datasheet(HTML) 4 Page - ON Semiconductor

   
 4 page
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MC100EPT24
http://onsemi.com
4
Table 6. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 4)
Symbol
Characteristic
−40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Input Clock Frequency (Fig-
ure 2)
> 1
> 1
> 1
GHz
tPLH,
tPHL
Propagation Delay to
Output Differential (Note 5)
300
500
800
300
530
800
300
560
800
ps
tJITTER
RMS Random Clock Jitter (Figure 2)
0.2
< 1
0.2
< 1
0.2
< 1
ps
tr
tf
Output Rise/Fall Times
Q, Q
(20% − 80%) @ 50 MHz
70
125
170
80
130
180
100
150
200
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured using a LVTTL source, 50% duty cycle clock source. All loading with 50 W to GND − 2.0 V.
5. Specifications for standard TTL input signal.
0
100
200
300
400
500
600
700
800
900
100
300
500
700
900
1100
1300
1
2
3
4
5
6
7
8
9
Figure 2. Output Voltage Amplitude (VOUTpp)/RMS Jitter
vs. Input Clock Frequency at Ambient Temperature
INPUT CLOCK FREQUENCY (MHz)
(JITTER)
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q
D
Zo = 50 W
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V


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