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MC100LVEL13DWR2G Datasheet(PDF) 2 Page - ON Semiconductor |
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MC100LVEL13DWR2G Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 6 page MC100LVEL13 http://onsemi.com 2 CLKa Figure 1. Logic Diagram and Pinout: 20−Lead SOIC (Top View) CLKa CLKb VCC 17 18 16 15 14 13 12 4 3 5 678 9 Q2a 11 10 Q2a VCC Q2b Q2b Q1b Q1b VEE Q0a 19 20 2 1 Q1a Q1a VCC CLKb Q0a Q0b Q0b Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Table 1. PIN DESCRIPTION FUNCTION ECL Differential Clock Outputs ECL Differential Clock Outputs ECL Differential Clock Inputs Positive Supply Negative Supply PIN Qna, Qna Qnb, Qnb CLKn, CLKn VCC VEE Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V VI VCC VI VEE 6 to 0 −6 to 0 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction to Ambient) 0 lfpm 500 lfpm 20 SOIC 20 SOIC 90 60 °C/W °C/W qJC Thermal Resistance (Junction to Case) Standard Board 20 SOIC 30 to 35 °C/W Tsol Wave Solder Pb Pb−Free <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. |
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