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CAT34RC02 Datasheet(PDF) 8 Page - Catalyst Semiconductor |
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CAT34RC02 Datasheet(HTML) 8 Page - Catalyst Semiconductor |
8 / 14 page Discontinued Part CAT34RC02 8 Doc. No. 1052, Rev. O © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Figure 10. Software Write Protect (Write) Figure 9. Memory Array * For PSWP A 0 is at normal CMOS levels and for RSWP, A0 is at VHV which must be held high beyond the end of the STOP condition (approximately 1 µs of “overlap” is sufficient). address counter can be ‘initialized’ by performing a ‘dummy’ WRITE operation (Fig. 12). The START condition is followed by the Slave address (with the R/ W bit set to ‘0’) and the desired byte address. Instead of following up with data, the Master then issues a 2nd START, followed by the ‘Immediate Address Read’ sequence, as described earlier. Software Write Protectable (by setting the write protect flags) FFH 00H 7FH Hardware Write Protectable (by connecting WP pin to Vcc) BYTE ADDRESS SLAVE ADDRESS S A C K A C K DATA A C K S T O P P BUS ACTIVITY: MASTER SDA LINE S T A R T XXXXXXX XXXXXXX X = Don't Care XX Sequential Read If the Master acknowledges the 1st data byte transmitted by the CAT34RC02, then the device will continue transmitting as long as each data byte is acknowledged by the Master (Fig. 13). If the end of memory is reached during sequential READ, the address counter will ‘wrap- around’ to the beginning of memory, etc. Sequential READ works with either ‘Immediate Address Read’ or ‘Selective Read’, the only difference being the starting byte address. |
Similar Part No. - CAT34RC02_05 |
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Similar Description - CAT34RC02_05 |
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