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CAT24WC6633XA-1.8T2C Datasheet(PDF) 6 Page - Catalyst Semiconductor

Part # CAT24WC6633XA-1.8T2C
Description  64K-bit I2C Serial EEPROM with Partial Array Write Protection
Download  13 Pages
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Manufacturer  CATALYST [Catalyst Semiconductor]
Direct Link  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT24WC6633XA-1.8T2C Datasheet(HTML) 6 Page - Catalyst Semiconductor

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CAT24WC66
Doc. No. 1037 Rev. J
6
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W
¯¯ bit set to zero) to the Slave device.
After the Slave generates an acknowledge, the Master
sends two 8-bit address words that are to be written
into the address pointers of the CAT24WC66. After
receiving another acknowledge from the Slave, the
Master device transmits the data to be written into the
addressed
memory
location.
The
CAT24WC66
acknowledges once more and the Master generates
the STOP condition. At this time, the device begins
an internal programming cycle to nonvolatile memory.
While the cycle is in progress, the device will not
respond to any request from the Master device.
Page Write
The CAT24WC66 writes up to 32 bytes of data, in a
single write cycle, using the Page Write operation.
The page write operation is initiated in the same
manner as the byte write operation, however instead
of terminating after the initial byte is transmitted, the
Master is allowed to send up to 31 additional bytes.
After each byte has been transmitted, CAT24WC66
will respond with an acknowledge, and internally
increment the five low order address bits by one. The
high order bits remain unchanged.
If the Master transmits more than 32 bytes before
sending the STOP condition, the address counter
‘wraps around’, and previously transmitted data will be
overwritten.
When all 32 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24WC66 in a single write cycle.
Acknowledge Polling
Disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition
is issued to indicate the end of the host's write
operation, CAT24WC66 initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the
slave address for a write operation. If CAT24WC66 is
still busy with the write operation, no ACK will be
returned. If CAT24WC66 has completed the write
operation, an ACK will be returned and the host can
then proceed with the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory
array. If the WP pin is tied to VCC, the top 1/4 of the
memory array (locations 1800H to 1FFF) is protected
and becomes read only. The CAT24WC66 will accept
both slave and byte addresses, but the memory
location accessed is protected from programming by
the device’s failure to send an acknowledge after the
first byte of data is received.
Figure 6. Byte Write Timing
Figure 7. Page Write Timing
X= Don't care bit
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
DATA
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A7–A0
BYTE ADDRESS
A
C
K
X
XX
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A7–A0
BYTE ADDRESS
DATA n+31
DATA
A
C
K
S
T
O
P
A
C
K
DATA n
A
C
K
P
A
C
K
X
XX


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