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Switching Characteristics

Operating Characteristics

Initial Activation Time

One of pins A9–A13 is switched as shown above, and the other four inputs are forced at low state.

TYP = 80 ns

SN74LVCZ161284A

19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER

WITH ERROR-FREE POWER UP

SCES358B – SEPTEMBER 2001 – REVISED MAY 2005

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2 and

Figure 3)

FROM

TO

PARAMETER

UNIT

(INPUT)

(OUTPUT)

1

22

Totem pole

A1–A8

B1–B8

ns

1

22

1

20

Totem pole

A9–A13

Y9–Y13

ns

1

20

1

10

Totem pole

B1–B8

A1–A8

ns

1

10

1

11

Totem pole

C14–C17

A14–A17

ns

1

11

1

13

Totem pole

PERI LOGIC IN

PERI LOGIC OUT

ns

1

13

1

13

Totem pole

HOST LOGIC IN

HOST LOGIC OUT

ns

1

13

Totem pole

B1–B8 and Y9–Y13 outputs

0.05

0.4

V/ns

1

20

B1–B8, Y9–Y13, and

HD

ns

PERI LOGIC OUT

1

15

DIR

A1–A8

1

15

ns

1

15

DIR

B1–B8

ns

1

15

Open drain

A1–A13

B1–B8 or Y9–Y13

1

120

ns

A1–A8 or B1–B8

B1–B8 or A1–A8

2.5

10

ns

(1)

(2)

V

PARAMETER

TEST CONDITIONS

TYP

UNIT

Power dissipation capacitance

Outputs enabled

f = 10 MHz

45

pF

Figure 1. Error-Free Circuit Timing

6