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MMUN2212LT1G Datasheet(PDF) 1 Page - ON Semiconductor |
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MMUN2212LT1G Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 12 page © Semiconductor Components Industries, LLC, 2005 August, 2005 − Rev. 7 Publication Order Number: MMUN2211LT1/D MMUN2211LT1 Series Preferred Devices Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base-emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. The device is housed in the SOT-23 package which is designed for low power surface mount applications. Features • Simplifies Circuit Design • Reduces Board Space and Component Count • Pb−Free Packages are Available MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Symbol Value Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc Collector Current IC 100 mAdc THERMAL CHARACTERISTICS Characteristic Symbol Max Unit Total Device Dissipation TA = 25°C Derate above 25 °C PD 246 (Note 1) 400 (Note 2) 1.5 (Note 1) 2.0 (Note 2) mW °C/W Thermal Resistance, Junction-to-Ambient RqJA 508 (Note 1) 311 (Note 2) °C/W Thermal Resistance, Junction-to-Lead RqJL 174 (Note 1) 208 (Note 2) °C/W Junction and Storage Temperature Range TJ, Tstg − 55 to +150 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. FR−4 @ minimum pad 2. FR−4 @ 1.0 x 1.0 inch pad SOT−23 CASE 318 STYLE 6 MARKING DIAGRAM PIN 3 COLLECTOR (OUTPUT) PIN 2 EMITTER (GROUND) PIN 1 BASE (INPUT) R1 R2 Preferred devices are recommended choices for future use and best overall value. http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. ORDERING INFORMATION A8x M G G 1 A8x = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) |
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