MC14517B

http://onsemi.com

3

Characteristic

Symbol

Min

Typ

(Note 6)

Max

Unit

Output Rise and Fall Time

5.0

10

15

−

−

−

100

50

40

200

100

80

ns

Propagation Delay Time

5.0

10

15

−

−

−

475

210

140

770

300

215

ns

Clock Pulse Width

5.0

10

15

330

125

100

170

75

60

−

−

−

ns

Clock Pulse Frequency

5.0

10

15

−

−

−

3.0

6.7

8.3

1.5

4.0

5.3

MHz

Clock Pulse Rise and Fall Time

5.0

10

15

See (Note 7)

−

Data to Clock Setup Time

5.0

10

15

0

10

15

– 40

– 15

0

−

−

−

ns

Data to Clock Hold Time

5.0

10

15

150

75

35

75

25

10

−

−

−

ns

Write Enable to Clock Setup Time

5.0

10

15

400

200

110

170

65

50

−

−

−

ns

Write Enable to Clock Release Time

5.0

10

15

380

180

100

160

55

40

−

−

−

ns

5. The formulas given are for the typical characteristics only at 25

_C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

7. When shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than the rise and fall

time of the data outputs, driving data inputs, plus the propagation delay of the output driving stage.

Figure 1. Power Dissipation Test Circuit and Waveform

Q16 Q32 Q48 Q64

Q16 Q32 Q48 Q64

D

C

WE

D

C

WE

D

C

50 mF

REPETITIVE WAVEFORM

C

D