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ADF4113HVBRUZ Datasheet(PDF) 4 Page - Analog Devices |
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ADF4113HVBRUZ Datasheet(HTML) 4 Page - Analog Devices |
4 / 20 page ADF4113HV Rev. 0 | Page 4 of 20 TIMING CHARACTERISTICS Guaranteed by design but not production tested. AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; 13.5 V ≤ VP ≤ 16.5 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments t1 20 ns min LE setup time t2 10 ns min DATA to CLK setup time t3 10 ns min DATA to CLK hold time t4 25 ns min CLK high duration t5 25 ns min CLK low duration t6 10 ns min CLK to LE setup time t7 20 ns min LE pulse width Timing Diagram CLK DATA LE LE DB23 (MSB) DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t1 t2 t3 t7 t6 t4 t5 Figure 2. Timing Diagram |
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