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AD8312ACBZ-P2 Datasheet(PDF) 7 Page - Analog Devices |
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AD8312ACBZ-P2 Datasheet(HTML) 7 Page - Analog Devices |
7 / 20 page AD8312 Rev. 0| Page 7 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 VPOS 6 RFIN 2 VOUT 5 COMM 3 VSET 4 CFLT AD8312 TOP VIEW (Not to Scale) Figure 2. Pin Configuration Table 3. Pin Function Descriptions Ball No. Mnemonic Description 1 VPOS Positive Supply Voltage (VS), 2.7 V to 5.5 V. 2 VOUT Logarithmic Output. Output voltage increases with increasing input amplitude. 3 VSET Setpoint Input. Connect VSET to VOUT for measurement-mode operation. The nominal logarithmic slope of 20 mV/dB can be increased to an arbitrarily high value by attenuating the signal between VOUT and VSET (see the Increasing the Logarithmic Slope section). 4 CFLT Connection for an External Capacitor to Slow the Response of the Output. Capacitor is connected between CFLT and VOUT. 5 COMM Device Common (Ground). 6 RFIN RF Input. |
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