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AT25160-10PI-2.7 Datasheet(PDF) 10 Page - ATMEL Corporation

Part # AT25160-10PI-2.7
Description  SPI Serial EEPROMs
Download  21 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT25160-10PI-2.7 Datasheet(HTML) 10 Page - ATMEL Corporation

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10
AT25080/160/320/640
0675M–SEEPR–9/03
READ SEQUENCE (READ): Reading the AT25080/160/320/640 via the SO (Serial Output)
pin requires the following sequence. After the CS line is pulled low to select a device, the
READ op-code is transmitted via the SI line followed by the byte address to be read (A15 - A0,
Refer to Table 6). Upon completion, any data on the SI line will be ignored. The data (D7 - D0)
at the specified address is then shifted out onto the SO line. If only one byte is to be read, the
CS line should be driven high after the data comes out. The READ sequence can be contin-
ued since the byte address is automatically incremented and data will continue to be shifted
out. When the highest address is reached, the address counter will roll over to the lowest
address allowing the entire memory to be read in one continuous READ cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25080/160/320/640, two separate
instructions must be executed. First, the device must be write enabled via the Write Enable
(WREN) Instruction. Then a Write (WRITE) Instruction may be executed. Also, the address of
the memory location(s) to be programmed must be outside the protected address field location
selected by the Block Write Protection Level. During an internal write cycle, all commands will
be ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After the CS line is pulled low to select the
device, the WRITE op-code is transmitted via the SI line followed by the byte address
(A15 - A0) and the data (D7 - D0) to be programmed (Refer to Table 6). Programming will start
after the CS pin is brought high. (The LOW-to-High transition of the CS pin must occur during
the SCK low-time immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a READ STATUS
REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0 = 0, the
WRITE cycle has ended. Only the READ STATUS REGISTER instruction is enabled during
the WRITE programming cycle.
The AT25080/160/320/640 is capable of a 32-byte PAGE WRITE operation. After each byte of
data is received, the five low order address bits are internally incremented by one; the high
order bits of the address will remain constant. If more than 32 bytes of data are transmitted,
the address counter will roll over and the previously written data will be overwritten. The
AT25080/160/320/640 is automatically returned to the write disable state at the completion of
a WRITE cycle.
NOTE: If the device is not Write enabled (WREN), the device will ignore the Write instruction
and will return to the standby state, when CS is brought high. A new CS falling edge is
required to re-initiate the serial communication.
Table 6. Address Key
Address
AT25080
AT25160
AT25320
AT25640
AN
A9 - A0
A10 - A0
A11 - A0
A12 - A0
Don't Care Bits
A15 - A10
A15 - A11
A15 - A12
A15 - A13


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