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NCP5201MNG Datasheet(PDF) 4 Page - ON Semiconductor |
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NCP5201MNG Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 9 page NCP5201 http://onsemi.com 4 ELECTRICAL CHARACTERISTICS (VSTBY = 5.0 V, VCC = 12 V, TA = 0 to 70°C, L2 = 1.7 mH, COUT = 3770 mF, COUT2 = 220 mF, RL1 = 100 k W, R7 = 1.0 kW, R10 = 1.0 k, R12 = 20 kW, R6 = 16 W, C12 = 3.0 nF, C11 = 6.0 nF, C10 = 80 nF, for min/max values unless otherwise noted) Characteristic Unit Max Typ Min Test Conditions Symbol CONTROL SECTION S3_EN Pin Threshold HIGH − S3_EN_H 1.4 − − V S3_EN Pin Threshold LOW − S3_EN_L − − 0.5 V S3_EN Pin Input Current − IIN_EN − − 0.5 mA PWRGD Pin ON Resistance − PWRGD_R − − 80 W PWRGD Pin OFF Current − PWRGD_ LEAK − − 1.0 mA PWRGD LOW−to−HIGH Hold Time, For S3 to S0 or S5 to S0 − thold − − 200 ms GATE DRIVERS TGDDQ Gate Pull−HIGH Resistance VCC = 12 V, V(TGDDQ) = 11 V RH_TG − 3.0 − W TGDDQ Gate Pull−LOW Resistance VCC = 12 V, V(TGDDQ) = 1.0 V RL_TG − 2.5 − W BGDDQ Gate Pull−HIGH Resistance VCC = 12 V, V(BGDDQ) = 11 V RH_BG − 3.0 − W BGDDQ Gate Pull−LOW Resistance VCC = 12 V, V(BGDDQ) = 1.0 V RL_BG − 1.3 − W PIN DESCRIPTION Pin No. Symbol Description 1 FBDDQ VDDQ feedback pin for closed loop regulation. 2 FBVTT VTT regulator sense voltage. 3 PGND Power ground. 4 VSTBY 5 V Standby input voltage. 5, 6 VTT VTT regulator output. 7 OCDDQ Overcurrent sense and program input for the VDDQ high−side FET. 8 VDDQ Reference input and power stage input for VTT regulator. 9 NC Not connected. 10 PWRGD Open drain status output. High impedance when the product is operating in S0 state and both DDQ and VTT regulators are in compliance. 11 S3_EN S3 mode enable input. High to enable. 12 AGND Analog ground connection and remote ground sense. 13 SDDQ Inductor driven node and current limit sense input. 14 BGDDQ Gate driver output, VDDQ Low−Side N−Channel Power FET. Active during S0 mode. 15 TGDDQ Gate driver output, VDDQ High−Side N−Channel Power FET. Active during S0 mode. 16 VCC 12 Volt input supply. This voltage is monitored by power good circuitry for mode selection. 17 COMP VDDQ error amplifier compensation node. 18 SS Soft−start capacitor connection to ground. 19 TH_PAD Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane under the IC. |
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