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NCP5422ADR2 Datasheet(PDF) 9 Page - ON Semiconductor |
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NCP5422ADR2 Datasheet(HTML) 9 Page - ON Semiconductor |
9 / 16 page NCP5422A, NCP5423 http://onsemi.com 9 Figure 6. Hiccup Overcurrent Protection Output Enable On/Off control of the regulator outputs can be implemented by pulling the COMP pins low. The COMP pins must be driven below the 0.425 V PWM comparator offset voltage in order to disable the switching of the GATE drivers. DESIGN GUIDELINES Definition of the design specifications The output voltage tolerance can be affected by any or all of the following reasons: 1. buck regulator output voltage setpoint accuracy; 2. output voltage change due to discharging or charging of the bulk decoupling capacitors during a load current transient; 3. output voltage change due to the ESR and ESL of the bulk and high frequency decoupling capacitors, circuit traces, and vias; 4. output voltage ripple and noise. Budgeting the tolerance is left up to the designer who must take into account all of the above effects and provide an output voltage that will meet the specified tolerance at the load. The designer must also ensure that the regulator component temperatures are kept within the manufacturer’s specified ratings at full load and maximum ambient temperature. Selecting Feedback Divider Resistors VOUT R1 R2 VFB Figure 7. Selecting Feedback Divider Resistors Selection of Feedback Divider Resistors Feedback divider resistors R1 and R2 are selected based on a design trade−off between efficiency and output voltage accuracy. Both error amplifiers are referenced to 1.0 V, and resistors R1 and R2 are connected from each channel’s output voltage to the inverting pin (VFB1(2)) of each error amplifier. To set the channel output voltage, first choose a value for R1, and then R2 can be sized as follows: R1 Vout 1.0 * 1 R2 + The output voltage error due to the bias current of the error amplifier and the parallel combination of R1 and R2 can now be estimated: Error + 1.6 · 10−6 · R1 · R2 R1 ) R2 Reducing the size of R1 and R2 will reduce the output voltage error, but increase the power dissipation. Calculating Duty Cycle The duty cycle of a buck converter (including parasitic losses) is given by the formula: Duty Cycle + D + VOUT ) VLFET ) VL VIN ) VLFET * VHFET where: VOUT = buck regulator output voltage; VHFET = high side FET voltage drop due to RDS(ON); VL = output inductor voltage drop due to inductor wire DC resistance; VIN = buck regulator input voltage; VLFET = low side FET voltage drop due to RDS(ON). |
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