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T89C51RB2-SLSCM Datasheet(PDF) 11 Page - ATMEL Corporation

Part # T89C51RB2-SLSCM
Description  8-bit Microcontroller with 16K/ 32K Bytes Flash
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

T89C51RB2-SLSCM Datasheet(HTML) 11 Page - ATMEL Corporation

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11
T89C51RB2/RC2
4105D–8051–10/06
Enhanced Features
In comparison to the original 80C52, the T89C51RB2/RC2 implements some new fea-
tures, which are:
the X2 option
the Dual Data Pointer
the extended RAM
the Programmable Counter Array (PCA)
the Hardware Watchdog
the SPI interface
the 4-level interrupt priority system
the power-off flag
the ONCE mode
the ALE disabling
some enhanced features are also located in the UART and the timer 2
X2 Feature
The T89C51RB2/RC2 core needs only 6 clock periods per machine cycle. This feature
called ‘X2’ provides the following advantages:
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
Save power consumption while keeping same CPU power (oscillator power saving).
Save power consumption by dividing dynamically the operating frequency by 2 in
operating and idle modes.
Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
Description
The clock for the whole circuit and peripherals is first divided by two before being used
by the CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 4 shows the clock generation block diagram. X2 bit is validated on the rising edge
of the XTAL1
÷2 to avoid glitches when switching from X2 to STD mode. Figure 5 shows
the switching mode waveforms.
Figure 4. Clock Generation Diagram
XTAL1
2
CKCON0
X2
8 bit Prescaler
FOSC
FXTAL
0
1
XTAL1:2
FCLK CPU
FCLK PERIPH
CKRL


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