3968

DUAL FULL-BRIDGE

PWM MOTOR DRIVER

WITH BRAKE

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

Load Current Regulation. Due to internal logic and

blanking time, limit the minimum value the current control

circuitry can regulate. To produce zero current in a

held high, turning off all output drivers for that H-bridge.

Logic Inputs. The direction of current in the motor

1.8 µs prevents cross-over current spikes that can occur

when switching the motor direction.

A logic high on both INPUTs turns off all four output

drivers of that H-bridge. This results in a fast current

decay through the internal ground clamp and flyback

diodes.

width modulated for applications that require a fast cur-

rent-decay PWM. The internal current-control logic can

will place that H-Bridge in the brake mode. Both source

drivers are turned OFF and both sink drivers are turned

ON. This has the effect of shorting the dc motor’s back-

EMF voltage, resulting in a current flow that dynamically

brakes the motor.

Note that during braking the internal current-control

circuitry is disabled. Therefore, care should be taken to

ensure that the motor’s current does not exceed the abso-

lute maximum rating of the A3968.

The REFERENCE input voltage is typically set with a

internally divided down by 4 to set up the current-com-

parator trip-voltage threshold. The reference input voltage

range is 0 to 2 V.

Output Drivers. To minimize on-chip power dissipa-

tion, the sink drivers incorporate a Satlington structure.

of a saturated transistor and the high peak-current capa-

bility of a Darlington (connected) transistor. A graph

showing typical output saturation voltages as a function

of output current is on the next page.

Miscellaneous Information. Thermal protection

circuitry turns off all output drivers should the junction

temperature reach +165°C (typical). This is intended

only to protect the device from failures due to excessive

junction temperatures and should not imply that output

short circuits are permitted. Normal operation is resumed

when the junction temperature has decreased about 15°C.

The A3968 current control employs a fixed-fre-

quency, variable duty cycle PWM technique. If the duty

cycle exceeds 50%, the current-control-regulation fre-

quency may change.

To minimize current-sensing inaccuracies caused by

should have a separate return to the ground terminal of

the device. For low-value sense resistors, the I x R drops

in the printed-wiring board can be significant and should

be taken into account. The use of sockets should be

avoided as their contact resistance can cause variations in

decoupled with an electrolytic capacitor (47 µF recom-

mended) placed as close to the device as physically

practical. To minimize the effect of system ground I x R

drops on the logic and reference input signals, the system

ground should have a low-resistance return to the load

supply voltage.

The frequency of the clock oscillator will determine

the amount of ripple current. A lower frequency will

result in higher current ripple, but reduced heating in the

motor and driver IC due to a corresponding decrease in

hysteretic core losses and switching losses respectively.

A higher frequency will reduce ripple current, but will

increase switching losses and EMI.

FUNCTIONAL DESCRIPTION (continued)