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RTL8201CL-VD Datasheet(PDF) 30 Page - Realtek Semiconductor Corp.

Part # RTL8201CL-VD
Description  SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER
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Manufacturer  REALTEK [Realtek Semiconductor Corp.]
Direct Link  https://www.realtek.com/en/
Logo REALTEK - Realtek Semiconductor Corp.

RTL8201CL-VD Datasheet(HTML) 30 Page - Realtek Semiconductor Corp.

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RTL8201CL
Datasheet
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
24
Track ID: JATR-1076-21 Rev. 1.24
Symbol
Condition
Minimum
Maximum
PECL VIH
PECL Input High Vol.
Vdd -1.16V
Vdd -0.88V
PECL VIL
PECL Input Low Vol.
Vdd -1.81V
Vdd -1.47V
PECL VOH
PECL Output High Vol.
Vdd -1.02V
PECL VOL
PECL Output Low Vol.
Vdd -1.62V
8.2. AC Characteristics
8.2.1.
MII Transmission Cycle Timing
Table 33. MII Transmission Cycle Timing
Symbol
Description
Minimum
Typical
Maximum
Unit
100Mbps
14
20
26
ns
t1
TXCLK high pulse width
10Mbps
140
200
260
ns
100Mbps
14
20
26
ns
t2
TXCLK low pulse width
10Mbps
140
200
260
ns
100Mbps
40
ns
t3
TXCLK period
10Mbps
400
ns
100Mbps
10
24
ns
t4
TXEN, TXD[0:3] setup to
TXCLK rising edge
10Mbps
5
ns
100Mbps
10
25
ns
t5
TXEN, TXD[0:3] hold after
TXCLK rising edge
10Mbps
5
ns
100Mbps
40
ns
t6
TXEN sampled to CRS high
10Mbps
400
ns
100Mbps
160
ns
t7
TXEN sampled to CRS low
10Mbps
2000
ns
100Mbps
60
70
140
ns
t8
Transmit latency
10Mbps
2000
ns
100Mbps
100
170
ns
t9
Sampled TXEN inactive to end
of frame
10Mbps
ns
Figure 6 shows an example of a packet transfer from MAC to PHY on the MII interface.
TXCLK
V
I H(min)
V
IL(max)
TXD[0:3]
TXEN
V
IH(min)
V
IL(max)
t4
t5
t3
t1
t2
Figure 6. MII Transmission Cycle Timing-1
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