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RTL8201CL-VD Datasheet(PDF) 14 Page - Realtek Semiconductor Corp.

Part # RTL8201CL-VD
Description  SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER
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Manufacturer  REALTEK [Realtek Semiconductor Corp.]
Direct Link  https://www.realtek.com/en/
Logo REALTEK - Realtek Semiconductor Corp.

RTL8201CL-VD Datasheet(HTML) 14 Page - Realtek Semiconductor Corp.

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RTL8201CL
Datasheet
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
8
Track ID: JATR-1076-21 Rev. 1.24
6. Register Descriptions
This section describes the functions and usage of the registers available in the RTL8201CL.
In this section the following abbreviations are used:
RO:
Read Only
RW:
Read/Write
6.1. Register 0 Basic Mode Control Register
Table 9. Register 0 Basic Mode Control Register
Address
Name
Description
Mode
Default
0:15
Reset
This bit sets the status and control registers of the PHY in a default
state. This bit is self-clearing.
1: Software reset
0: Normal operation
RW
0
0:14
Loopback
This bit enables loopback of transmit data nibbles TXD3:0 to the
receive data path.
1: Enable loopback
0: Normal operation
RW
0
0:13
Spd_Set
This bit sets the network speed.
1: 100Mbps
0: 10Mbps
After completing auto negotiation, this bit will reflect the Speed status.
1: 100Base-T
0: 10Base-T)
When 100Base-FX mode is enabled, this bit=1 and is read only.
RW
0
0:12
Auto
Negotiation
Enable
This bit enables/disables the NWay auto-negotiation function.
1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored.
0: Disable auto-negotiation; bits 0:13 and 0:8 will determine the link
speed and the data transfer mode, respectively.
When 100Base-FX mode is enabled, this bit=0 and is read only.
RW
1
0:11
Power Down This bit turns down the power of the PHY chip, including the internal
crystal oscillator circuit. The MDC, MDIO is still alive for accessing
the MAC.
1: Power down
0: Normal operation
RW
0
0:10
Reserved
0:9
Restart Auto
Negotiation
This bits allows the NWay auto-negotiation function to be reset.
1: Re-start auto-negotiation
0: Normal operation
RW
0
0:8
Duplex
Mode
This bit sets the duplex mode if auto-negotiation is disabled
(bit 0:12=0).
1: Full duplex
0: Half duplex
After completing auto-negotiation, this bit will reflect the duplex
status.
1: Full duplex
0: Half duplex
RW
0
0:7:0
Reserved
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