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A3995 Datasheet(PDF) 4 Page - Allegro MicroSystems

Part No. A3995
Description  DMOS Dual Full Bridge PWM Motor Driver
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Manufacturer  ALLEGRO [Allegro MicroSystems]
Direct Link  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

A3995 Datasheet(HTML) 4 Page - Allegro MicroSystems

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DMOS Dual Full Bridge PWM Motor Driver
A3995
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
ELECTRICAL CHARACTERISTICS1, valid at TA = 25 °C, VBB = 36 V, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Load Supply Voltage Range
VBB
Operating
8.0
36
V
Logic Supply Voltage Range
VDD
Operating
3.0
5.5
V
VDD Supply Current
IDD
7
10
mA
Output On Resistance
RDS(on)
Source driver, IOUT = –1. A, TJ = 5°C
350
450
Sink driver, IOUT = 1. A, TJ = 5°C
350
450
Vf, Outputs
IOUT = 1. A
1.
V
Output Leakage
IDSS
Outputs, VOUT = 0 to VBB
–0
0
µA
VBB Supply Current
IBB
IOUT = 0 mA, outputs on, PWM = 50 kHz,
DC = 50%
8
mA
Control Logic
Logic Input Voltage
VIN(1)
0.7×VDD
V
VIN(0)
0.3×VDD
V
Logic Input Current
IIN
VIN = 0 to 5 V
–0
<1.0
0
µA
Input Hysteresis
Vhys
150
300
500
mV
Propagation Delay Times
tpd
PWM change to source on
350
550
1000
ns
PWM change to source off
35
300
ns
PWM change to sink on
350
550
1000
ns
PWM change to sink off
35
50
ns
Crossover Delay
tCOD
300
45
1000
ns
Blank Time
tBLANK
.5
3.
4
µs
VREFx Pin Input Voltage Range
VREFx
Operating
0.0
1.5
V
VREFx Pin Reference Input Current
IREF
VREF = 1.5
±1
μA
Protection Circuits
VBB UVLO Threshold
VUV(VBB)
VBB rising
7.3
7.6
7.9
V
VBB Hysteresis
VUV(VBB)hys
400
500
600
mV
VDD UVLO Threshold
VUV(VDD)
VDD rising
.65
.8
.95
V
VDD Hysteresis
VUV(VDD)hys
75
105
15
mV
Thermal Shutdown Temperature
TJTSD
155
165
175
°C
Thermal Shutdown Hysteresis
TJTSDhys
15
°C
1
For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.

Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for indi-
vidual units, within the specified maximum and minimum limits.
3
VERR = [(VREF/3) – VSENSE] / (VREF/3).
DC Control Logic
PHASE
ENABLE
MODE
OUTA
OUTB
Function
1
1
1
H
L
Forward (slow decay SR)
1
1
0
H
L
Forward (fast decay SR)
0
1
1
L
H
Reverse (slow decay SR)
0
1
0
L
H
Reverse (fast decay SR)
X
0
1
L
L
Brake (slow decay SR)
1
0
0
L
H
Fast decay SR*
0
0
0
H
L
Fast decay SR*
* To prevent reversal of current during fast decay SR – the outputs will go to the high impedance state as the current gets near zero.


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