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FDS8812NZ Datasheet(PDF) 2 Page - Fairchild Semiconductor

Part # FDS8812NZ
Description  N-Channel PowerTrench MOSFET 30V, 20A, 4.0mohm
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FDS8812NZ Datasheet(HTML) 2 Page - Fairchild Semiconductor

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FDS8812NZ Rev.C
www.fairchildsemi.com
2
Electrical Characteristics T
J = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250μA, VGS = 0V
30
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250μA, referenced to 25°C
19
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS = 24V, VGS = 0V
1
μA
IGSS
Gate to Source Leakage Current
VGS = ±20V, VDS = 0V
±10
μA
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250μA
1
1.8
3
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250μA, referenced to 25°C
–7
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS = 10V, ID = 20A
3.1
4.0
m
Ω
VGS = 4.5V, ID = 18A
3.8
4.9
VGS = 10V, ID = 20A, TJ = 125°C
4.2
5.3
gFS
Forward Transconductance
VDS = 5V, ID = 20A
87
S
(Note 2)
Dynamic Characteristics
Ciss
Input Capacitance
VDS = 15V, VGS = 0V,
f = 1MHz
5205
6925
pF
Coss
Output Capacitance
945
1260
pF
Crss
Reverse Transfer Capacitance
580
870
pF
Rg
Gate Resistance
f = 1MHz
1.5
Ω
Switching Characteristics
td(on)
Turn-On Delay Time
VDD = 15V, ID = 20A
VGS = 10V, RGEN = 6Ω
18
33
ns
tr
Rise Time
13
24
ns
td(off)
Turn-Off Delay Time
55
88
ns
tf
Fall Time
12
22
ns
Qg
Total Gate Charge
VGS = 0V to 10V
VDD = 15V
ID = 20A
90
126
nC
Qg
Total Gate Charge
VGS = 0V to 5V
49
69
nC
Qgs
Gate to Source Charge
16
nC
Qgd
Gate to Drain “Miller” Charge
18
nC
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage
VGS = 0V, IS = 2.1A
(Note 2)
0.7
1.2
V
trr
Reverse Recovery Time
IF = 20A, di/dt = 100A/μs
36
54
ns
Qrr
Reverse Recovery Charge
33
50
nC
Notes:
1. RθJA is the sum of the junction-to-case and case-to- ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain
pins. RθJC is guaranteed by design while RθJA is determined by the user’s board design.
2. Pulse Test: Pulse Width < 300 us, Duty Cycle < 2%.
3. The diode connected between the gate and source serves only as protection against ESD . No gate overvoltage rating is implied.
4. Starting TJ = 25°C, L = 3mH, IAS = 21A, VDD = 30V, VGS = 10V.
a) 50°C/W when mounted on a
1in2 pad of 2 oz copper.
b) 125°C/W when mounted on a
minimum pad .


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