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CC1010 Datasheet(PDF) 70 Page - Texas Instruments |
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CC1010 Datasheet(HTML) 70 Page - Texas Instruments |
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70 / 152 page  CC1010 SWRS047 Page 70 of 152 received stop bit is stored in RB8_0 / RB8_1) and the receive interrupt flag is set. If not, the received data is lost and RB8_0 / RB8_1 and the receive interrupt flag remains unchanged. 16.7.3 MODE2 Mode 2 provides asynchronous full-duplex communication using a total of 11 bits: 1 start bit, 8 data bits, a programmable 9th bit and 1 stop bit. The data bits are transmitted and received LSB first. The mode 2 baud rate is either fsystem/32 or fsystem/64, set by PCON.SMOD0 (or EICON.SMOD1). The baud rate is then: system f Rate Baud ⋅ = 64 2SMODx To transmit data in mode 1, write data to SBUF0 / SBUF1. Transmission is then performed on pin TXD0 / TXD1 in the following order: start bit, 8 data bits (LSB first), 9th bit (from TB8_0 / TB8_1) and then the stop bit. The transmit interrupt flag TI_0 / TI_1 is set when the stop bit is placed on the transmit pin. Reception must be enabled by setting REN_0 / REN_1. It is then initiated by the falling edge of a start bit received on RXD0 / RXD1. The input pin is sampled 16 times per baud. Majority decision is made, as with mode 1. When the majority decision is made for the stop-bit, the following conditions must be met: • RI_0 / RI_1 is 0 • If SM2_0 / SM2_1 is set, the 9th bit and the stop bit must be one. If these conditions are met, the received data is buffered in SBUF0 / SBUF1, the received stop bit is stored in RB8_0 / RB8_1 and the receive interrupt flag RI_0 / RI_1 is set. If not, the received data is lost and RB8 and the receive interrupt flag remains unchanged. 16.7.4 MODE 3 Mode 3 provides asynchronous, full- duplex communication, using a total of 11 bits (as with mode 2): 1 start bit, 8 data bits, a programmable 9th bit and 1 stop bit. The data bits are transmitted and received LSB first. Transmission and reception in mode 3 is identical to mode 2, except for the baud rate generation, which is identical to mode 1. 16.7.5 Multiprocessor Communications The multiprocessor communication feature is enabled in mode2 and mode 3, when the SM2_0 / SM2_1 bit is set. The 9th bit received is then stored in RB8_0 / RB8_1 and the interrupt bit is only set if this bit is 1. An address byte can then be transmitted, with the 9th bit set, to generate an interrupt on all slaves. The slave(s) with the correct address (decoded in software) may then clear SM2_0 / SM2_1 to receive the rest of the data, which is transmitted with the 9th bit low. All other slaves will then ignore the data received. |
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