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BQ2084DBT-V143G4 Datasheet(PDF) 5 Page - Texas Instruments |
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BQ2084DBT-V143G4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 69 page www.ti.com SMBus TIMING DIAGRAMS bq2084-V143 SLUS732 – SEPTEMBER 2006 SMBus TIMING SPECIFICATIONS (continued) V DD = 3 V to 3.6 V, TA = -20°C to 85°C unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(HIGH) Clock high period See (2) 4 50 µs tLOW:SEXT) Cumulative clock low slave extend time See (3) 25 ms tLOW:MEXT Cumulative clock low master extend time See (4) 10 ms tf Clock/data fall time (VILMAX – 0.15 V) to (VIHMIN + 0.15 V) 300 ns tr Clock/data rise time 0.9 VDD to (VILMAX– 0.15 V) 1000 ns (2) t(HIGH) Max. is minimum bus idle time. SMBC = 1 for t > 50 ms causes reset of any transaction involving bq2084-V143 that is in progress. (3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. (4) t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop. 5 Submit Documentation Feedback |
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