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CA3130E Datasheet(PDF) 4 Page - Intersil Corporation |
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CA3130E Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 17 page 4 Schematic Diagram Application Information Circuit Description Figure 1 is a block diagram of the CA3130 Series CMOS Operational Amplifiers. The input terminals may be operated down to 0.5V below the negative supply rail, and the output can be swung very close to either supply rail in many applications. Consequently, the CA3130 Series circuits are ideal for single-supply operation. Three Class A amplifier stages, having the individual gain capability and current consumption shown in Figure 1, provide the total gain of the CA3130. A biasing circuit provides two potentials for common use in the first and second stages. Terminal 8 can be used both for phase compensation and to strobe the output stage into quiescence. When Terminal 8 is tied to the negative supply rail (Terminal 4) by mechanical or electrical means, the output potential at Terminal 6 essentially rises to the positive supply-rail potential at Terminal 7. This condition of essentially zero current drain in the output stage under the strobed “OFF” condition can only be achieved when the ohmic load resistance presented to the amplifier is very high (e.g.,when the amplifier output is used to drive CMOS digital circuits in Comparator applications). Input Stage The circuit of the CA3130 is shown in the schematic diagram. It consists of a differential-input stage using PMOS field-effect transistors (Q6, Q7) working into a mirror-pair of bipolar transistors (Q9, Q10) functioning as load resistors together with resistors R3 through R6. The mirror-pair transistors also function as a differential-to- single-ended converter to provide base drive to the second- stage bipolar transistor (Q11). Offset nulling, when desired, can be effected by connecting a 100,000 Ω potentiometer across Terminals 1 and 5 and the potentiometer slider arm to Terminal 4. 3 2 1 8 4 6 7 Q1 Q2 Q4 D1 D2 D3 D4 Q3 Q5 D5 D6 D7 D8 Q9 Q10 Q6 Q7 5 Z1 8.3V INPUT STAGE R3 1k Ω R4 1k Ω R6 1k Ω R5 1k Ω NON-INV. INPUT INV.-INPUT + - R1 40k Ω 5k Ω R2 BIAS CIRCUIT CURRENT SOURCE FOR “CURRENT SOURCE LOAD” FOR Q11 Q6 AND Q7 V+ OUTPUT OUTPUT STAGE Q8 Q12 V- Q11 SECOND STAGE OFFSET NULL COMPENSATION STROBING (NOTE 5) NOTE: 5. Diodes D5 through D8 provide gate-oxide protection for MOSFET input stage. CA3130, CA3130A |
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