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CA3162 Datasheet(PDF) 4 Page - Intersil Corporation |
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CA3162 Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 7 page 4 Timing Diagram Detailed Description The Functional Block Diagram of the CA3162E shows the V/I converter and reference current generator, which is the heart of the system. The V/I converter converts the input voltage applied between pins 10 and 11 to a current that charges the integrating capacitor on pin 12 for a predetermined time inter- val. At the end of the charging interval, the V/I converter is dis- connected from the integrating capacitor, and a band gap reference constant current source of opposite polarity is connected. The number of clock counts that elapse before the charge is restored to its original value is a direct measure of the signal induced current. The restoration is sensed by the comparator, which in turn latches the counter. The count is then multiplexed to the BCD outputs. The timing for the CA3162E is supplied by a 786Hz ring oscillator, and the input at pin 6 determines the sampling rate. A 5V input provides a high speed sampling rate (96Hz), and grounding or floating pin 6 provides a low speed (4Hz) sam- pling rate. When pin 6 is fixed at +1.2V (by placing a 12K resistor between pin 6 and the +5V supply) a “hold” feature is available. While the CA3162E is in the hold mode, sampling continues at 4Hz but the display data are latched to the last reading prior to the application of the 1.2V. Removal of the 1.2V restores continuous display changes. Note, however, that the sampling rate remains at 4Hz. Figure 1 shows the timing of sampling and digit select pulses for the high speed mode. Note that the basic A/D conversion process requires approximately 5ms in both modes. The “EEE” or “---” displays indicate that the range of the system has been exceeded in the positive or negative direction, respectively. Negative voltages to -99mV are displayed with the minus sign in the MSD. The BCD code is 1010 for a negative overrange (---) and 1011 for a positive overrange (EEE). 2ms/DIV. 200mV 500mV 500mV 500mV 5(LSD) 4(MSD) 3 (NSD) 12 FIGURE 1. HIGH SPEED MODE FIGURE 2. BASIC DIGITAL READOUT SYSTEM USING THE CA3162E AND THE CA3161E NOTES: 1. The capacitor used here must be a low dielectric absorption type such as a polyester or polystyrene type. 2. This capacitor should be placed as close as possible to the power and ground Pins of the CA3161E. CA3161E 10 6 2 1 7 7 13 16 15 1 2 10 k Ω 3 8 10 9 15 14 11 12 13 GAIN ADJ R1 150 Ω R2 150 Ω R3 150 Ω MSD NSD LSD BCD DIGIT INPUTS HIGH LOW OUTPUTS DRIVERS 4 5 3 16 11 6 NORMAL LOW SPEED MODE: V6 = GROUND OR OPEN HOLD: V6 =1.2V HIGH SPEED MODE: V6 =5V CA3162E 8 12 9 14 0.27 µF 0.1 µF NOTE 1 NOTE 2 +5V COMMON ANODE LED DISPLAYS POWER 2N2907, 2N3906 OR EQUIV. 1k Ω DIGIT DRIVER CA3162E PINS 3, 4, 5 75 Ω BCD SEGMENT DRIVERS CA3162E PINS 1, 2, 15, 16 a b c d f g e a b c d f g e a b c d f g e CA3162 |
Similar Part No. - CA3162_02 |
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Similar Description - CA3162_02 |
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