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CS82C59AZ Datasheet(PDF) 9 Page - Intersil Corporation |
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CS82C59AZ Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 22 page 9 FN2784.5 March 17, 2006 e. If lC4 = 0, then all functions selected in lCW4 are set to zero. (Non-Buffered mode (see note), no Auto-EOI, 8080/85 system). NOTE: Master/Slave in ICW4 is only used in the buffered mode. Initialization Command Words 1 and 2 (ICW1, lCW2) A5 - A15: Page starting address of service routines. In an 8080/85 system the 8 request levels will generate CALLS to 8 locations equally spaced in memory. These can be programmed to be spaced at intervals of 4 or 8 memory locations, thus, the 8 routines will occupy a page of 32 or 64 bytes, respectively. The address format is 2 bytes long (A0 - A15). When the routine interval is 4, A0 - A4 are automatically inserted by the 82C59A, while A5 - A15 are programmed externally. When the routine interval is 8, A0 - A5 are automatically inserted by the 82C59A while A6 - A15 are programmed externally. The 8-byte interval will maintain compatibility with current software, while the 4-byte interval is best for a compact jump table. In an 80C86/88/286 system, A15 - A11 are inserted in the five most significant bits of the vectoring byte and the 82C59A sets the three least significant bits according to the interrupt level. A10 - A5 are ignored and ADI (Address interval) has no effect. LTlM: If LTlM = 1, then the 82C59A will operate in the level interrupt mode. Edge detect logic on the interrupt inputs will be disabled. ADI: ALL address interval. ADI = 1 then interval = 4; ADI = 0 then interval = 8. SNGL: Single. Means that this is the only 82C59A in the system. If SNGL = 1, no ICW3 will be issued. IC4: If this bit is set - lCW4 has to be issued. If lCW4 is not needed, set lC4 = 0. Initialization Command Word 3 (ICW3) This word is read only when there is more than one 82C59A in the system and cascading is used, in which case SNGL = 0. It will load the 8-bit slave register. The functions of this register are: a. In the master mode (either when SP = 1, or in buffered mode when M/S = 1 in lCW4) a “1” is set for each slave in the bit corresponding to the appropriate IR line for the slave. The master then will release byte 1 of the call sequence (for 8080/85 system) and will enable the corre- sponding slave to release bytes 2 and 3 (for 80C86/88/ 286, only byte 2) through the cascade lines. b. In the slave mode (either when SP = 0, or if BUF = 1 and M/S = 0 in lCW4), bits 2 - 0 identify the slave. The slave compares its cascade input with these bits and if they are equal, bytes 2 and 3 of the call sequence (or just byte 2 for 80C86/88/286) are released by it on the Data Bus. NOTE: (The slave address must correspond to the IR line it is connected to in the master ID). Initialization Command Word 4 (ICW4) SFNM: If SFNM = 1, the special fully nested mode is pro- grammed. BUF: If BUF = 1, the buffered mode is programmed. In buffered mode, SP/EN becomes an enable output and the master/slave determination is by M/S. M/S: If buffered mode is selected: M/S = 1 means the 82C59A is programmed to be a master, M/S = 0 means the 82C59A is programmed to be a slave. If BUF = 0, M/S has no function. AEOI: If AEOI = 1, the automatic end of interrupt mode is programmed. µPM: Microprocessor mode: µPM = 0 sets the 82C59A for 8080/85 system operation, µPM = 1 sets the 82C59A for 80C86/88/286 system operation. ICW1 ICW2 IN CASCADE MODE ICW3 IS ICW4 NEEDED ICW4 READY TO ACCEPT INTERRUPT REQUESTS NO (SNGL = 1) YES (SNGL = 0)) YES (IC4 = 1) NO (IC4 = 0) FIGURE 6. 82C59A INITIALIZATION SEQUENCE 82C59A 82C59A |
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